In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. A dual port (DP) SRAM device allows parallel operation, such as 1R (read) 1W (write), or 2R (read) in one cycle, and therefore has higher bandwidth than a single port SRAM. In advanced technologies with decreased feature size and increased packing density, low loading and high speed of the cell structure are important factors in embedded memory and SOC products. The thin style SRAM cell structure with short bit-line (BL) provides better performance on BL RC delay. For example, the thin style SRAM cell provides active regions, gates and metal lines with shapes friendly to lithography processes. However, the thin style cell has long word line. The length ratio of word line over bit line (WL/BL) is usually greater than 2 or even 3. In a dual port SRAM cell, the ratio WL/BL is even greater than 3.5. This short bit line can only benefits metal layer coupling capacitance but coupling capacitances associated with the front end of line (such as active regions and gates) and the middle end of line (such as contacts) are not improved. This even becomes a speed-limiting factor when it is used in fin field effect transistors (FinFETs) with long contact structure. This structure suffers various problems, such as long including data node leakage; devices matching of pull-down (PD)/pass-gate (PG) devices; and current crowding, etc. It is therefore desired to have a new structure and method to address the above issues.